In the wideband code division multiple access (i.e., WCDMA) standard, orthogonal variable spreading factor (i.e., OVSF) sequences are used to distinguish multiple users. Several common implementations exist to generate an OVSF sequence for a user when a sequence index of the user is known. Some common implementations are sequential and thus generate only a single bit of the sequence per cycle. The single bit per cycle techniques are suitable in cases where slow bit processing rates are acceptable.
In cases utilizing fast processing rates, a whole OVSF sequence (i.e., 256 bits) or even several OVSF sequences should be generated in a single cycle. To achieve the fast processing rate, a timing of the sequence generation should be minimized. The common implementations utilize additional levels of exclusive OR gates (i.e., XOR gates) for each doubling of the OVSF sequence length. A known process to generate a single OVSF sequence having bits B0 . . . B(L-1) based on a sequence index having bits A0 . . . A(N-1) is described as follows. The number of different OVSF sequences that could be generated depends on a spreading factor (i.e., L). The spreading factor L represents the number of bits in each sequence and is a power of 2 (i.e., L=2N). Usually, the value N belongs to a range 1≦N≦8. The first four bits of the sequence are calculated as:B0=1;B1=NOT(A0);B2=NOT(A1); andB3=XOR(A1, B1),where “1” represents a logical one and NOT is a logical inversion. Calculation of the next 4 bits depends on the previous 4 bits:B4 . . . B7=XOR(B0 . . . B3, A2).Calculation of the next 8 bits depends on the previous 8 bits:B8 . . . B15=XOR(B0 . . . B7, A3).Calculation of the next 16 bits depends on the previous 16 bits:B16 . . . B31=XOR(B0 . . . B15, A4).
The common methods generate a 4-bit length OVSF sequence by implementing a level of XOR gates after a level of NOT gates. Generation of an 8-bit length OVSF sequence is implemented as two levels of XOR gates after the level of NOT gates. Generation of a 256-bit length OVSF sequence is implemented as 7 levels of XOR gates after the level of NOT gates. Each level of XOR gates increases a timing delay of the OVSF sequence generation process, thus decreasing the maximum possible calculation frequency. In modern hardware systems, additional operations are commonly performed after the OVSF sequence is generated in the same clock cycle as the OVSF sequence generation. Therefore, a reduction of every XOR gate level increases the maximum possible calculation frequency.
Some conventional implementations slightly reduce the number of XOR gate levels. However, such implementations increase the number of overall XOR gates. The increased number of gates increases a chip area of the design and increases a power consumption.
It would be desirable to implement orthogonal variable spreading factor code sequence generation.